? semiconductor components industries, llc, 2005 january, 2005 ? rev. 5 1 publication order number: sg3525a/d sg3525a pulse width modulator control circuit the sg3525a pulse width modulator control circuit offers improved performance and lower external parts count when implemented for controlling all types of switching power supplies. the on?chip +5.1 v reference is trimmed to 1% and the error amplifier has an input common?mode voltage range that includes the reference voltage, thus eliminating the need for external divider resistors. a sync input to the oscillator enables multiple units to be slaved or a single unit to be synchronized to an external system clock. a wide range of deadtime can be programmed by a single resistor connected between the c t and discharge pins. this device also features built?in soft?start circuitry, requiring only an external timing capacitor. a shutdown pin controls both the soft?start circuitry and the output stages, providing instantaneous turn off through the pwm latch with pulsed shutdown, as well as soft?start recycle with longer shutdown commands. the under voltage lockout inhibits the outputs and the changing of the soft?start capacitor when v cc is below nominal. the output stages are totem?pole design capable of sinking and sourcing in excess of 200 ma. the output stage of the sg3525a features nor logic resulting in a low output for an off?state. features ? 8.0 v to 35 v operation ? 5.1 v 1.0% trimmed reference ? 100 hz to 400 khz oscillator range ? separate oscillator sync pin ? adjustable deadtime control ? input undervoltage lockout ? latching pwm to prevent multiple pulses ? pulse?by?pulse shutdown ? dual source/sink outputs: 400 ma peak ? pb?free packages are available* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. marking diagrams a = assembly location wl = wafer lot yy = year ww = work week 1 16 pdip?16 n suffix case 648 1 16 sg3525an awlyyww pin connections 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 (top view) inv. input sync osc. output r t discharge soft-start noninv. input c t compensation shutdown output a v c output b v cc v ref ground 1 16 sg3525a awlyyww soic?16l dw suffix case 751g see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information 16 1 http://onsemi.com
sg3525a http://onsemi.com 2 figure 1. representative block diagram nor nor 16 15 12 4 3 6 5 7 9 1 2 8 10 reference regulator under- voltage lockout oscillator latch f/f q q - pwm error amp + - + - to internal circuitry v ref v ref v cc ground osc output sync rt ct discharge compensation inv. input noninv. input c soft-start shutdown 5.0k s r s 50 a vc 13 output a 11 14 output b sg3525a output stage 5.0k ordering information device package shipping 2 sg3525an pdip?16 25 units / rail sg3525ang pdip?16 (pb?free) 25 units / rail sg3525adw soic?16l 47 units / rail sg3525adwg soic?16l (pb?free) 47 units / rail SG3525ADWR2 soic?16l 1000 tape & reel SG3525ADWR2g soic?16l (pb?free) 1000 tape & reel 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
sg3525a http://onsemi.com 3 maximum ratings rating symbol value unit supply voltage v cc +40 vdc collector supply voltage v c +40 vdc logic inputs ?0.3 to +5.5 v analog inputs ?0.3 to v cc v output current, source or sink i o 500 ma reference output current i ref 50 ma oscillator charging current 5.0 ma power dissipation t a = +25 c (note 1) t c = +25 c (note 2) p d 1000 2000 mw thermal resistance, junction?to?air r ja 100 c/w thermal resistance, junction?to?case r jc 60 c/w operating junction temperature t j +150 c storage temperature range t stg ?55 to +125 c lead temperature (soldering, 10 seconds) t solder +300 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. derate at 10 mw/ c for ambient temperatures above +50 c. 2. derate at 16 mw/ c for case temperatures above +25 c. recommended operating conditions characteristics symbol min max unit supply voltage v cc 8.0 35 vdc collector supply voltage v c 4.5 35 vdc output sink/source current (steady state) (peak) i o 0 0 100 400 ma reference load current i ref 0 20 ma oscillator frequency range f osc 0.1 400 khz oscillator timing resistor r t 2.0 150 k oscillator timing capacitor c t 0.001 0.2 f deadtime resistor range r d 0 500 operating ambient temperature range t a 0 +70 c application information shutdown options (see block diagram, page 2) since both the compensation and soft?start terminals (pins 9 and 8) have current source pull?ups, either can readily accept a pull?down signal which only has to sink a maximum of 100 a to turn off the outputs. this is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. an alternate approach is the use of the shutdown circuitry of pin 10 which has been improved to enhance the available shutdown options. activating this circuit by applying a positive signal on pin 10 performs two functions: the pwm latch is immediately set providing the fastest turn?off signal to the outputs; and a 150 a current sink begins to discharge the external soft?start capacitor. if the shutdown command is short, the pwm signal is terminated without significant discharge of the soft?start capacitor, thus, allowing, for example, a convenient implementation of pulse?by?pulse current limiting. holding pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn?on upon release. pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation.
sg3525a http://onsemi.com 4 electrical characteristics (v cc = +20 vdc, t a = t low to t high [note 3], unless otherwise noted.) characteristics symbol min typ max unit reference section reference output voltage (t j = +25 c) v ref 5.00 5.10 5.20 vdc line regulation (+8.0 v v cc +35 v) reg line ? 10 20 mv load regulation (0 ma i l 20 ma) reg load ? 20 50 mv temperature stability v ref / t ? 20 ? mv total output variation includes line and load regulation over temperature v ref 4.95 ? 5.25 vdc short circuit current (v ref = 0 v, t j = +25 c) i sc ? 80 100 ma output noise voltage (10 hz f 10 khz, t j = +25 c) v n ? 40 200 v rms long term stability (t j = +125 c) (note 4) s ? 20 50 mv/khr oscillator section (note 5, unless otherwise noted.) initial accuracy (t j = +25 c) ? 2.0 6.0 % frequency stability with voltage (+8.0 v v cc +35 v) f osc d vcc ? 1.0 2.0 % frequency stability with temperature f osc d t ? 0.3 ? % minimum frequency (r t = 150 k , c t = 0.2 f) f min ? 50 ? hz maximum frequency (r t = 2.0 k , c t = 1.0 nf) f max 400 ? ? khz current mirror (i rt = 2.0 ma) 1.7 2.0 2.2 ma clock amplitude 3.0 3.5 ? v clock width (t j = +25 c) 0.3 0.5 1.0 s sync threshold 1.2 2.0 2.8 v sync input current (sync voltage = +3.5 v) ? 1.0 2.5 ma error amplifier section (v cm = +5.1 v) input offset voltage v io ? 2.0 10 mv input bias current i ib ? 1.0 10 a input offset current i io ? ? 1.0 a dc open loop gain (r l 10 m ) a vol 60 75 ? db low level output voltage v ol ? 0.2 0.5 v high level output voltage v oh 3.8 5.6 ? v common mode rejection ratio (+1.5 v v cm +5.2 v) cmrr 60 75 ? db power supply rejection ratio (+8.0 v v cc +35 v) psrr 50 60 ? db pwm comparator section minimum duty cycle dc min ? ? 0 % maximum duty cycle dc max 45 49 ? % input threshold, zero duty cycle (note 5) v th 0.6 0.9 ? v input threshold, maximum duty cycle (note 5) v th ? 3.3 3.6 v input bias current i ib ? 0.05 1.0 a 3. t low = 0 t high = +70 c 4. since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability from lot to lot. 5. tested at f osc = 40 khz (r t = 3.6 k , c t = 0.01 f, r d = 0 ).
sg3525a http://onsemi.com 5 electrical characteristics (continued) characteristics symbol min typ max unit soft?start section soft?start current (v shutdown = 0 v) 25 50 80 a soft?start voltage (v shutdown = 2.0 v) ? 0.4 0.6 v shutdown input current (v shutdown = 2.5 v) ? 0.4 1.0 ma output drivers (each output, v cc = +20 v) output low level (i sink = 20 ma) (i sink = 100 ma) v ol ? ? 0.2 1.0 0.4 2.0 v output high level (i source = 20 ma) (i source = 100 ma) v oh 18 17 19 18 ? ? v under voltage lockout (v8 and v9 = high) v ul 6.0 7.0 8.0 v collector leakage, v c = +35 v (note 6) i c(leak) ? ? 200 a rise time (c l = 1.0 nf, t j = 25 c) t r ? 100 600 ns fall time (c l = 1.0 nf, t j = 25 c) t f ? 50 300 ns shutdown delay (v ds = +3.0 v, c s = 0, t j = +25 c) t ds ? 0.2 0.5 s supply current (v cc = +35 v) i cc ? 14 20 ma 6. applies to sg3525a only, due to polarity of output pulses. reference regulator flip/ flop pwm - + e/a dut v ref clock 16 4 0.1 3 6 7 5 deadtime 100 0.001 comp 10k 9 0.01 1 2 1 2 3 1 2 3 3 2 1 3 + - 1 = v io 2 = 1(+) 3 = 1(-) 0.1 0.009 1.5k 1.0k 3.0k pwm adj. sync rt ramp 50 a 5.0k 5.0k 15 13 11 v c out a 0.1 0.1 1.0k, 1.0w (2) 14 out b gnd 12 8 softstart 5.0 f 10 2.0k shutdown v ref + o s c i l l a t o r v/i meter v cc a 1 2 b figure 2. lab test fixture
sg3525a http://onsemi.com 6 r t w , timing resistor (k ) figure 3. oscillator charge time versus r t figure 4. oscillator discharge time versus r d figure 5. error amplifier open loop frequency response figure 6. output saturation characteristics 2.0 5.0 10 20 50 100 200 500 1000 2000 5000 10,000 charge time ( s) 6 57 r d * c t r t * r d = 0 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 discharge time ( s) , dead time resistor () d w r 1.0 10 100 1.0 k 10 k 100 k 1.0 m 10 m 1 2 9 c p r z f, frequency (hz) , voltage gain (db) vol - + a r z = 20 k v ref r t c t sync discharge gnd 16 6 5 3 7 12 q2 q1 q6 q9 2.0k 2.0k 14k q10 q11 5.0pf 400 a 23k q4 q7 1.0k q12 q13 3.0k 250 4 blanking to output ramp to pwm q14 25k 7.4k q5 q8 q3 osc output 1.0k 15 q3 v cc 9 30 compensation 1 2 q4 q1 q2 inverting input 5.8v 100 a to pwm comparator 200 a noninverting input figure 7. oscillator schematic 0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 i o, output source or sink current (a) , saturation voltage (v) sat v sink sat, (v ol ) source sat, (v c -v oh ) v cc = +20 v t j = +25 c figure 8. error amplifier schematic 200 100 50 20 10 5.0 2.0 500 400 300 200 100 0 100 80 60 40 20 0 -20 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
sg3525a http://onsemi.com 7 figure 9. output circuit (1/2 circuit shown) figure 10. single?ended supply figure 11. push?pull configuration figure 12. driving power fets low power transformers can be driven directly by the sg3525a. automatic reset occurs during deadtime, when both ends of the primary winding are switched to ground. q1 r1 r2 13 to output filter 11 14 12 v c sg3525a a b gnd + v supply for single-ended supplies, the driver outputs are grounded. the v c terminal is switched to ground by the totem-pole source transistors on alternate oscillator cycles. in conventional push-pull bipolar designs, forward base drive is controlled by r1-r3. rapid turn-off times for the power devices are achieved with speed-up capacitors c1 and c2. v c sg3525a a b gnd +v supply r1 13 12 11 14 r3 c2 c1 q1 q2 t1 r2 the low source impedance of the output drivers provides rapid charging of power fet input capacitance while minimizing external components. + v supply v c sg3525a a b gnd 11 14 q1 q2 t1 r1 13 12 v c sg3525a a b gnd 13 11 14 12 +v supply t1 q1 q2 r2 r1 t2 c1 c2 figure 13. driving transformers in a half?bridge configuration q3 v cc q5 q4 q7 q9 q10 13 v c v ref q1 q2 q6 omitted in sg3527a 5.0k 10k 10k 2.0k q11 q6 q8 5.0k 11, 14 output clock f/f pwm
sg3525a http://onsemi.com 8 package dimensions pdip?16 n suffix case 648?08 issue t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ?a? b f c s h g d j l m 16 pl seating 18 9 16 k plane ?t? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
sg3525a http://onsemi.com 9 package dimensions soic?16l dw suffix case 751g?03 issue c d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 q 0 7
sg3525a http://onsemi.com 10 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 sg3525a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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